The present invention relates to a clock generator.
It has been known that a clock signal or a data signal changing synchronously with the clock signal generates electromagnetic interference, hereinafter referred to as “EMI”. In recent years, the required frequency of a clock signal becomes higher and measures against EMI are in demand.
To suppress EMI noise, there has been proposed a spread spectrum clock generator (SSCG) which gives minute oscillations to the clock frequency relative to a clock signal resulting in noise and reduce the strength (amplitude) of a noise spectrum by means of a smoothing action with the oscillations.
However, the conventional SSCG uses a PLL circuit, which causes a function of SSCG to come into no action until the PLL circuit has stabilized and is unsuitable to a system which frequently switches turning on and off a power supply. There is also a problem of a cost increase due to use of a PLL circuit.
As a SSCG having no PLL circuit, there has been proposed an apparatus which gives oscillations to a reference frequency by inputting an input pulse (a clock signal of the reference frequency) into a delay circuit including a plurality of delay buffers connected in series and outputting an output of the delay buffer selected by switching as needed as an output pulse.
It has been known that what has a large effect in EMI noise reduction is the one that gives periodical waveform fluctuations to a reference clock, such as Hershey Kiss waveform. The apparatus described above has a reference frequency as an output pulse during a period except instantaneous switching period of a delay time (selected delay buffer) and therefore an EMI reduction effect is small.
Accordingly, there has been requested a clock generator which has a simple circuit configuration without PLL circuit and can generate a clock signal having a steadily oscillating frequency.